1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for forming improved transistors that have improved high frequency response.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density and device performance in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced while increasing the performance of the devices.
Transistor performance is of particular concern in bipolar transistor design. Bipolar transistors are commonly used for analog devices where operational speed is of paramount concern. There are many different critical features in the design of high performance bipolar transistors. These include the vertical dimension of the bipolar transistor, the collector doping, collector-base and base-emitter capacitances, and collector and base resistances. To achieve higher performance, it is generally desirable to reduce the vertical dimension of the transistor. This reduces the transit time and thus can increase performance. Also, it is generally desirable to increase the collector doping concentration. This reduces collector resistance and thus can also increase performance. These goals are generally compatible, as a vertical dimension reduction is achieved partly by the increase in collector doping concentration since the collector-base space-charge region shrinks with higher doping concentrations.
Unfortunately, simply reducing transistor vertical dimension and increasing the collector doping concentration has the negative result of increasing collector-base capacitance. The increase in collector-base capacitance has a negative impact on the performance of the device, and thus can negate the benefits of reducing the vertical dimension and increasing collector doping concentration.
Thus, what is needed is an improved device structure and method that improves transistor performance with minimal increase of unwanted capacitance in the device. Without an improved method and structure for forming such devices the performance of these devices will continue to be compromised.
Accordingly, the present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a stepped collector dopant profile that reduces emitter-collector transit time and parasitic resistance with minimal increase in parasitic capacitances. The preferred stepped collector dopant profile includes a shallow implant and a deeper implant. The shallow implant reduces the base-collector space-charge region width, reduces resistance, and tailors the collector-base characteristics. The deeper implant links the buried collector to the subcollector and provides a low resistance path to the subcollector. The stepped collector dopant profile has minimal impact on the collector-base capacitance outside the intrinsic region of the device since the higher dopant is compensated by, or buried in, the extrinsic base dopants outside the intrinsic region.
The foregoing and other advantages and features of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.